{"id":119,"date":"2020-11-09T13:21:59","date_gmt":"2020-11-09T13:21:59","guid":{"rendered":"http:\/\/learnlearn.uk\/igcsecs\/?page_id=119"},"modified":"2022-01-25T07:30:53","modified_gmt":"2022-01-25T07:30:53","slug":"von-neumann-architecture","status":"publish","type":"page","link":"https:\/\/learnlearn.uk\/igcsecs\/von-neumann-architecture\/","title":{"rendered":"Von Neumann Architecture"},"content":{"rendered":"<div class=\"responsive-tabs\">\n<h2 class=\"tabtitle\">Introduction<\/h2>\n<div class=\"tabcontent\">\n\n<div class=\"arconix-column-two-thirds\">\n<h2><b>Von Neumann Architecture<\/b><\/h2>\n<p>The first computers had fixed programs and changing a computer program required physically rewiring or redesigning the machine. This meant that re-repurposing an computer was a difficult, expensive and time-consuming process. The Mathematician John Von-Neuman designed the specification for the first programmable computer in 1954, where the programs themselves could be stored in memory, not just data.<\/p>\n<p>Instructions are stored in memory and are retrieved and processed by the Central Processing Unit one by one. This blueprint is known as the Von-Neumann Architecture.<\/p>\n<p>The Von-Neuman Architecture is based on the principle of:<\/p>\n<ul>\n<li>Fetch an Instruction<\/li>\n<li>Decode the Instruction<\/li>\n<li>Execute the Instruction<\/li>\n<\/ul>\n<p>The process above is repeated indefinitely, and is known as the fetch, decode, execute cycle.<\/p>\n<\/div>\n<div class=\"arconix-column-one-third\">\n<p><a href=\"http:\/\/learnlearn.uk\/gcsecs\/wp-content\/uploads\/sites\/8\/2018\/01\/von-neumann-architecture-gcse-ocr.png\"><img decoding=\"async\" loading=\"lazy\" class=\"alignnone wp-image-448 size-medium\" src=\"https:\/\/learnlearn.uk\/gcsecs\/wp-content\/uploads\/sites\/8\/2018\/01\/von-neumann-architecture-gcse-ocr-300x206.png?_t=1516712389\" alt=\"Von Neumann Architecture OCR GCSE\" width=\"300\" height=\"206\" \/><\/a><\/p>\n<\/div>\n<p>&nbsp;<\/p>\n<p>\n<\/div><h2 class=\"tabtitle\">Video<\/h2>\n<div class=\"tabcontent\">\n<br \/>\n<iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/t8H6-anK0t4\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\" data-mce-fragment=\"1\"><\/iframe><\/p>\n<p><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/ckDb_W72__c\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\" data-mce-fragment=\"1\"><\/iframe><\/p>\n<p><a href=\"https:\/\/docs.google.com\/presentation\/d\/1OKFAkxq21fWd66dFKjgI859zh2QwO1Yl84N3N09nnTY\/edit?usp=sharing\">The Google Slides blank document to follow along with the video is available here.<\/a><\/p>\n\n<\/div><h2 class=\"tabtitle\">CU<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Control Unit (CU)<\/h3>\n<p>The job of the control unit is to coordinate and control all the other parts of the CPU. It tells the registers &amp; ALU what to do with an instruction that is passed to them.<\/p>\n<p>The CU decodes the instructions retrieved from memory and instructs the ALU to perform an arithmetic or logic instruction on the data from the decoded instruction<\/p>\n\n<\/div><h2 class=\"tabtitle\">ALU<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Arithmetic Logic Unit<\/h3>\n<p>They job of the ALU is to perform the calculations or logic that the CU has decoded.<\/p>\n<p>Common processes include:<\/p>\n<ul>\n<li>Addition<\/li>\n<li>Subtraction<\/li>\n<li>Division<\/li>\n<li>Multiplication<\/li>\n<li>Selection \/ Branching<\/li>\n<li>Repetition \/ looping.<\/li>\n<\/ul>\n\n<\/div><h2 class=\"tabtitle\">Registers<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Registers<\/h3>\n<p>The registers form part of the CPU Cache, temporarily storing data ready for processing or send to the RAM.<\/p>\n<p><strong>PC &#8211; Program Control Register<\/strong><\/p>\n<p>The program control register stores the address of the current instruction. Once the current instruction has been <strong>fetched<\/strong> and <strong>decoded,<\/strong> the program control register changes to the address of the next instruction.<\/p>\n<p><strong>IR &#8211; Instruction Register<\/strong><\/p>\n<p>The instruction register contains the current instruction itself, retrieved from it&#8217;s stored address.<\/p>\n<p><strong>MAR &#8211; Memory Address Register<\/strong><\/p>\n<p>The memory address register contains the memory location of either the next instruction to be fetched or the location of where the results of the current process are to be stored.<\/p>\n<p><strong>MDR &#8211; Memory Data Register<\/strong><\/p>\n<p>The memory data register contains either the data retrieved from memory (either an instruction or an operand) during the current fetch cycle at the address stipulated in the MAR, or the data the is due to be written to memory.<\/p>\n<p><strong>ACC &#8211; Accumulator<\/strong><\/p>\n<p>The accumulator receives the results of the current process from the ALU and stores it for the use in the next Fetch-Decode-Execute cycle.<\/p>\n\n<\/div><h2 class=\"tabtitle\">Buses<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Buses<\/h3>\n<p>Buses are the physical wires along which data is passed, both within the CPU itself and across the motherboard.<\/p>\n<p><strong>CPU Bus<\/strong><\/p>\n<p>The CPU bus is used to pass data around the CPU between the CU,ALU and reigsters.<\/p>\n<p><strong>Control Bus<\/strong><\/p>\n<p>The Control bu sends signals to the RAM, indicating whether to initiate a read or write on the address recieved along te address bus<\/p>\n<p><strong>Address Bus\u00a0<\/strong><\/p>\n<p>The address bus is the wire along which the address of the memory location in RAM required for the read\/write is sent.<\/p>\n<p><strong>Data Bus<\/strong><\/p>\n<p>The data bus is the wire along which the data is sent either to or from the RAM (depending whether a read or write has been initiated.<\/p>\n<p>&nbsp;<\/p>\n<p>\n<\/div><h2 class=\"tabtitle\">Review Quiz<\/h2>\n<div class=\"tabcontent\">\n<br \/>\n<iframe loading=\"lazy\" src=\"https:\/\/docs.google.com\/forms\/d\/e\/1FAIpQLSeowzqDlwRytvJAUdEQAhx6aCd0zNabS5yqM1Ana4621AH2lg\/viewform?embedded=true\" width=\"760\" height=\"1000\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" data-mce-fragment=\"1\">Loading&#8230;<\/iframe><\/p>\n\n<\/div><h2 class=\"tabtitle\">Resources<\/h2>\n<div class=\"tabcontent\">\n\n<p>Make a copy of this Google Slides ( File &gt; Make a copy ) and fill in the blanks from the video<\/p>\n<a href='https:\/\/docs.google.com\/presentation\/d\/1bOP_A9T9UaucJ6Nxf9bkKSqlmiphyN2Kc_4X9YSBHho\/edit?usp=sharing' class='arconix-button arconix-button-medium arconix-button-gray'>Von Neuman Blank Copy <\/a>\n<p><strong>Past Paper Questions<\/strong><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2015-jun-0478-s15-qp-11-pdf\">0478\/11 Paper 1 Theory May\/June 2015 &#8211; Qn 7<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2016-nov-0478-w16-qp-11-pdf\">0478\/11 &#8211; Paper 1 Theory October\/November 2016 Qn1<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2016-nov-0478-w16-qp-12-pdf\">0478\/12 &#8211; Paper 1 Theory October\/November 2016 Qn6<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2016-nov-0478-w16-qp-13-pdf\">Fetch Execute Cycle &#8211;\u00a00478\/13 &#8211; Paper 1 Theory October\/November 2016 Qn1<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2017-jun-0478-s17-qp-11-pdf\">0478\/11 &#8211; Paper 1 Theory May\/June 2017 Qn 6<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2017-jun-0478-s17-qp-11-pdf\">0478\/11 Paper 1 Theory May\/June 2017 qn 6\u00a0<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2017-nov-0478-w17-qp-11-pdf\">0478\/11 &#8211; Paper 1 Theory October\/November 2017 qn4<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2018-march-0478-m18-qp-12-pdf\">0478\/12 Paper 1 Theory February\/March 2018 Qn10<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/viewer\/caie\/cambridge-upper-secondary-igcse-computer-science-0478-2018-may-june-0478-s18-qp-12-pdf\">0478\/12 &#8211; Paper 1 Theory May\/June 2018 Qn6 &#8211; fill in the blanks<\/a><\/p>\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; The Google Slides blank document to follow along with the video is available here. Control Unit (CU) The job of the control unit is to coordinate and control all the other parts of the CPU. It tells the registers &amp; ALU what to do with an instruction that is passed to them. The CU&hellip;&nbsp;<a href=\"https:\/\/learnlearn.uk\/igcsecs\/von-neumann-architecture\/\" class=\"\" rel=\"bookmark\">Read More &raquo;<span class=\"screen-reader-text\">Von Neumann Architecture<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"","neve_meta_content_width":70,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Von Neumann Architecture | IGCSE Computer Science | Learnlearn.uk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/learnlearn.uk\/igcsecs\/von-neumann-architecture\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Von Neumann Architecture | IGCSE Computer Science | Learnlearn.uk\" \/>\n<meta property=\"og:description\" content=\"&nbsp; The Google Slides blank document to follow along with the video is available here. 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Control Unit (CU) The job of the control unit is to coordinate and control all the other parts of the CPU. It tells the registers &amp; ALU what to do with an instruction that is passed to them. The CU&hellip;&nbsp;Read&hellip;","_links":{"self":[{"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/pages\/119"}],"collection":[{"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/comments?post=119"}],"version-history":[{"count":12,"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/pages\/119\/revisions"}],"predecessor-version":[{"id":639,"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/pages\/119\/revisions\/639"}],"wp:attachment":[{"href":"https:\/\/learnlearn.uk\/igcsecs\/wp-json\/wp\/v2\/media?parent=119"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}