{"id":1119,"date":"2024-04-05T07:24:59","date_gmt":"2024-04-05T07:24:59","guid":{"rendered":"https:\/\/learnlearn.uk\/ibcs\/?page_id=1119"},"modified":"2025-04-05T11:21:51","modified_gmt":"2025-04-05T11:21:51","slug":"virtual-memory-paging","status":"publish","type":"page","link":"https:\/\/learnlearn.uk\/ibcs\/virtual-memory-paging\/","title":{"rendered":"Virtual Memory & Paging"},"content":{"rendered":"

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Introduction<\/h2>\n
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Virtual Memory Paging<\/h2>\n

Memory paging is a memory management technique used to control sharing of memory resources belonging to a computer or virtual machine (VM).<\/p>\n

In this scheme, the operating system retrieves data from secondary storage in same-size blocks called pages.<\/p>\n

A computer can address memory beyond the amount physically installed on the system. This non-physical memory, or virtual memory, is actually a section of a hard disk set up to emulate the computer’s RAM.<\/p>\n\n<\/div>

Address Spaces<\/h2>\n
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Virtual Address Spaces<\/h2>\n

A virtual address space is the set of ranges of virtual addresses that an operating system makes available to a process (max 64 bits on a 64 bit OS) .<\/p>\n

Each process has its own virtual address space that is distinct from other processes.<\/p>\n

This provides several benefits, one of which is security through process isolation assuming each process is given a separate address space.<\/p>\n

Physical Address space<\/h2>\n

When a process is loaded into RAM the virtual address space is mapped to a physical address space of the same size.<\/p>\n

The physical address space might be non-contiguous, meaning each page could be physically located in different parts of the RAM.<\/p>\n

The mapping assignments are recorded in the page table.<\/p>\n\n<\/div>

Page Table<\/h2>\n
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Page Table<\/h2>\n

The page table is a data structure used by a virtual memory system in a computer to store mappings between virtual addresses and physical addresses.<\/p>\n

The page table is set up by the computer’s operating system, and may be read and written by the memory management unit (MMU) or by low-level system software or firmware during the virtual address translation process .<\/p>\n

Physically, the memory of each process may be dispersed across different areas of physical memory, or may have been moved (paged out) to secondary storage, typically to a hard disk drive (HDD) or solid-state drive (SSD).<\/p>\n

However every process is given the impression that it is working with large, contiguous sections of memory.<\/p>\n\n<\/div>

MMU<\/h2>\n
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Memory Management Unit (MMU)<\/h2>\n

The MMU maps the virtual addresses from each program into separate areas in physical memory, which is generally much smaller than the theoretical maximum.<\/p>\n

This means that programs generally have addresses that access the theoretical maximum memory of the computer architecture, 32 or 64 bits.<\/p>\n

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TLB<\/h2>\n
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Translation Lookaside Buffer<\/h2>\n

The Translation Lookaside Buffer (TLB) is a a small, fast memory cache that stores recently used mappings between virtual addresses and their corresponding physical addresses.<\/p>\n

Once the translation information is retrieved, a new TLB entry is created using this information. This typically includes the virtual address, the corresponding physical address, and additional control bits such as access permissions.<\/p>\n

If the TLB is full and there is no space for the new entry, a replacement policy is used to select an existing entry to be evicted from the TLB to make room for the new entry.<\/p>\n

Common replacement policies include least recently used (LRU), random replacement, or first-in-first-out (FIFO).<\/p>\n

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Page Fault \/ Miss<\/h2>\n
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Page Fault \/ Page Table Miss<\/h2>\n

A page fault is an exception that the memory management unit (MMU) raises when a process accesses a memory page without proper preparations .<\/p>\n

The MMU raises the exception and the operating system’s kernel handles the exception by loading the requested page into RAM or denying an illegal memory access.<\/p>\n\n<\/div>

Steps<\/h2>\n
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Step 1 – Search the TLB<\/h2>\n

When a virtual address needs to be translated into a physical address, the Translation Lookaside Buffer is searched first.<\/p>\n

If a match is found, which is known as a TLB hit, the physical address is returned and memory access can continue.<\/p>\n

Step 2 – Walking the Page Table<\/h2>\n

However, if there is no match this results in a TLB miss.<\/p>\n

The MMU, the system firmware, or the operating system’s TLB miss handler will look up the address mapping in the page table to see whether a mapping exists.<\/p>\n

This is known as a page walk.<\/p>\n

Step 3 – Write Back to TLB<\/h2>\n

If the memory mapping exists, it is written back to the TLB and the faulting instruction is restarted.<\/p>\n

The subsequent translation will result in a TLB hit, and the memory access will continue.<\/p>\n

Step 4 – Page Fault<\/h2>\n

If the page is not in RAM (because it had been paged out onto secondary storage) this will result in a page table miss, triggering a page fault).<\/p>\n

Step 5 – Paging In<\/h2>\n

The process is not currently stored in RAM and therefore the system will need to load the process back into RAM (paged in).<\/p>\n

Stage 6 – Paging Out<\/h2>\n

Other data in the RAM may need to be paged out the Secondary Storage.<\/p>\n

Step 7 – Page Table Update & Process Restart<\/h2>\n

Finally the page table and TLB are updated the process is restarted.<\/p>\n

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Video<\/h2>\n
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https:\/\/www.youtube.com\/watch?v=8yO2FBBfaB0<\/a>