{"id":1179,"date":"2020-11-12T21:48:10","date_gmt":"2020-11-12T21:48:10","guid":{"rendered":"http:\/\/learnlearn.uk\/alevelcs\/?page_id=1179"},"modified":"2020-11-16T06:00:56","modified_gmt":"2020-11-16T06:00:56","slug":"risc-vs-cisc-processors","status":"publish","type":"page","link":"https:\/\/learnlearn.uk\/alevelcs\/risc-vs-cisc-processors\/","title":{"rendered":"RISC vs CISC Processors"},"content":{"rendered":"<div class=\"responsive-tabs\">\n<h2 class=\"tabtitle\">Video<\/h2>\n<div class=\"tabcontent\">\n\n<div class=\"nv-iframe-embed\">\n<div class=\"container-lazyload preview-lazyload container-youtube js-lazyload--not-loaded\"><a href=\"https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs\" class=\"lazy-load-youtube preview-lazyload preview-youtube\" data-video-title=\"6. OCR A Level (H046-H446) SLR2 - 1.1 CISC vs RISC\" title=\"Play video &quot;6. OCR A Level (H046-H446) SLR2 - 1.1 CISC vs RISC&quot;\">https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs<\/a><noscript>Video can&#8217;t be loaded because JavaScript is disabled: <a href=\"https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs\" title=\"6. OCR A Level (H046-H446) SLR2 - 1.1 CISC vs RISC\">6. OCR A Level (H046-H446) SLR2 &#8211; 1.1 CISC vs RISC (https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs)<\/a><\/noscript><\/div>\n<\/div>\n\n<\/div><h2 class=\"tabtitle\">RISC<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Reduced Instruction Set Computer<\/h3>\n<p>The RISC architecture was designed to prioritise processor efficiency and the expense programmer ease of use. This meant that they tended toward usage where efficiency is paramount.<\/p>\n<p><strong>Key Features<\/strong><\/p>\n<ul>\n<li>Commonly used in Smartphones (ARM\/Snapdragon Processors), some supercomputers<\/li>\n<li>Machine oriented<\/li>\n<li>1 Instruction per cycle<\/li>\n<li>Fixed Instruction Size in memory so we can use pipelining<\/li>\n<li>RISC does not do any operations directly in memory<\/li>\n<li>Highly efficient &amp; optimised &#8211; Low power consumption<\/li>\n<li>Many more lines of code<\/li>\n<li>Each task is broken into simple instructions<\/li>\n<li>Extensive use of general purpose registers<\/li>\n<li>Simplified instruction set<\/li>\n<li>Few addressing modes available<\/li>\n<\/ul>\n<p><strong>Example RISC Multiply Instruction<\/strong><\/p>\n<div id=\"attachment_1180\" style=\"width: 503px\" class=\"wp-caption alignnone\"><img aria-describedby=\"caption-attachment-1180\" decoding=\"async\" loading=\"lazy\" class=\"size-full wp-image-1180\" src=\"https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/RISC-instruction-example.png\" alt=\"\" width=\"493\" height=\"342\" srcset=\"https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/RISC-instruction-example.png 493w, https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/RISC-instruction-example-300x208.png 300w\" sizes=\"(max-width: 493px) 100vw, 493px\" \/><p id=\"caption-attachment-1180\" class=\"wp-caption-text\">Multiplying two numbers in memory requires 2 lines of code.<\/p><\/div>\n\n<\/div><h2 class=\"tabtitle\">CISC<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Complex Instruction Set Computer<\/h3>\n<p>The CISC architecture sacrifices some processor efficiency for the sake of ease of development and flexibility.<\/p>\n<ul>\n<li>Commonly Used in desktops and servers (Intel Processors)<\/li>\n<li>Programmer oriented<\/li>\n<li>Variable Instruction sizes in memory<\/li>\n<li>Processes more complex instructions<\/li>\n<li>1 Instructions may take more than one cycle<\/li>\n<li>Many addressing modes available<\/li>\n<\/ul>\n<p><strong>Example CISC Multiply Instruction<\/strong><\/p>\n<div id=\"attachment_1181\" style=\"width: 499px\" class=\"wp-caption alignnone\"><img aria-describedby=\"caption-attachment-1181\" decoding=\"async\" loading=\"lazy\" class=\"size-full wp-image-1181\" src=\"https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/CISC-Instruction-example.png\" alt=\"\" width=\"489\" height=\"155\" srcset=\"https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/CISC-Instruction-example.png 489w, https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/CISC-Instruction-example-300x95.png 300w\" sizes=\"(max-width: 489px) 100vw, 489px\" \/><p id=\"caption-attachment-1181\" class=\"wp-caption-text\">Multiplying 2 numbers in memory requires only 1 line of code.<\/p><\/div>\n\n<\/div><h2 class=\"tabtitle\">Interrupt Handling<\/h2>\n<div class=\"tabcontent\">\n\n<div class=\"nv-iframe-embed\">\n<div class=\"container-lazyload preview-lazyload container-youtube js-lazyload--not-loaded\"><a href=\"https:\/\/www.youtube.com\/watch?v=L8PhZ27ymt4\" class=\"lazy-load-youtube preview-lazyload preview-youtube\" data-video-title=\"Interrupt Handling on CISC &amp; RISC | A Level | By ZAK\" title=\"Play video &quot;Interrupt Handling on CISC &amp; RISC | A Level | By ZAK&quot;\">https:\/\/www.youtube.com\/watch?v=L8PhZ27ymt4<\/a><noscript>Video can&#8217;t be loaded because JavaScript is disabled: <a href=\"https:\/\/www.youtube.com\/watch?v=L8PhZ27ymt4\" title=\"Interrupt Handling on CISC &amp; RISC | A Level | By ZAK\">Interrupt Handling on CISC &amp; RISC | A Level | By ZAK (https:\/\/www.youtube.com\/watch?v=L8PhZ27ymt4)<\/a><\/noscript><\/div>\n<\/div>\n\n<\/div><h2 class=\"tabtitle\">Challenge<\/h2>\n<div class=\"tabcontent\">\n\n<h3>Programming Challenge<\/h3>\n<p>Today&#8217;s challenge is to create a quiz in Python. For each question the program should display a statement about RISC\/CISC architecture. The user needs to read the statement and decide which one it applies to.<\/p>\n<ul>\n<li>The quiz should have a time limit.<\/li>\n<li>The quiz statements should be loaded from a CSV file.<\/li>\n<li>The quiz should display how many questions they got right within the time limit, accuracy, answers per second, display a list of statements that were wrong.<\/li>\n<li>The quiz should store player names and scores.<\/li>\n<li>The quiz should display high scores.<\/li>\n<\/ul>\n\n<\/div><h2 class=\"tabtitle\">Resources<\/h2>\n<div class=\"tabcontent\">\n\n<p><a href=\"https:\/\/www.youtube.com\/watch?v=_EKgwOAAWZA\">Youtube Video<\/a><\/p>\n<p><a href=\"https:\/\/pastpapers.papacambridge.com\/view.php?id=Cambridge%20International%20Examinations%20%28CIE%29\/AS%20and%20A%20Level\/Computer%20Science%20-%209608\/2015%20Nov\/9608_w15_qp_31.pdf\">Past Paper Qns W15 Paper 31 Qn 4<\/a><\/p>\n<p><a href=\"https:\/\/www.elprocus.com\/what-is-risc-and-cisc-architecture-and-their-workings\/\">More info on RISC vs CSIC<\/a><\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<\/div><\/div>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJsVideo can&#8217;t be loaded because JavaScript is disabled: 6. OCR A Level (H046-H446) SLR2 &#8211; 1.1 CISC vs RISC (https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs) Reduced Instruction Set Computer The RISC architecture was designed to prioritise processor efficiency and the expense programmer ease of use. This meant that they tended toward usage where efficiency is paramount. Key Features Commonly used&hellip;&nbsp;<a href=\"https:\/\/learnlearn.uk\/alevelcs\/risc-vs-cisc-processors\/\" class=\"\" rel=\"bookmark\">Read More &raquo;<span class=\"screen-reader-text\">RISC vs CISC Processors<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"","neve_meta_content_width":70,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>RISC vs CISC Processors - A Level Computer Science<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/learnlearn.uk\/alevelcs\/risc-vs-cisc-processors\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RISC vs CISC Processors - A Level Computer Science\" \/>\n<meta property=\"og:description\" content=\"https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJsVideo can&#8217;t be loaded because JavaScript is disabled: 6. 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OCR A Level (H046-H446) SLR2 &#8211; 1.1 CISC vs RISC (https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs) Reduced Instruction Set Computer The RISC architecture was designed to prioritise processor efficiency and the expense programmer ease of use. This meant that they tended toward usage where efficiency is paramount. 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