{"version":"1.0","provider_name":"A Level Computer Science","provider_url":"https:\/\/learnlearn.uk\/alevelcs","author_name":"learnlearnadmin","author_url":"https:\/\/learnlearn.uk\/alevelcs\/author\/learnlearnadmin\/","title":"RISC vs CISC Processors - A Level Computer Science","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"bIDsirUJva\"><a href=\"https:\/\/learnlearn.uk\/alevelcs\/risc-vs-cisc-processors\/\">RISC vs CISC Processors<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/learnlearn.uk\/alevelcs\/risc-vs-cisc-processors\/embed\/#?secret=bIDsirUJva\" width=\"600\" height=\"338\" title=\"&#8220;RISC vs CISC Processors&#8221; &#8212; A Level Computer Science\" data-secret=\"bIDsirUJva\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script>\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/\/# sourceURL=https:\/\/learnlearn.uk\/alevelcs\/wp-includes\/js\/wp-embed.min.js\n<\/script>\n","description":"https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJsVideo can&#8217;t be loaded because JavaScript is disabled: 6. OCR A Level (H046-H446) SLR2 &#8211; 1.1 CISC vs RISC (https:\/\/www.youtube.com\/watch?v=PaeXsm5HGJs) Reduced Instruction Set Computer The RISC architecture was designed to prioritise processor efficiency and the expense programmer ease of use. This meant that they tended toward usage where efficiency is paramount. Key Features Commonly used&hellip;&nbsp;Read More &raquo;","thumbnail_url":"https:\/\/learnlearn.uk\/alevelcs\/wp-content\/uploads\/sites\/20\/2020\/11\/RISC-instruction-example.png"}